Bipolar memory cells are circuits wherein information may be stored in a low current standby mode and may be written into or read from in a higher current mode.
Many current bipolar memory cells comprise a pair of cross coupled multi-emitter transistors operating as a latch such as the transistors 2, 4 shown in FIG. 1. The bases 6, 8 of the transistors are cross coupled to each others' collectors 10, 12. A first emitter 14, 16 of each transistor is coupled to a standby current drain line 17. A second emitter 18 of one transistor is connected to a first bit line 20 and a second emitter 22 of the second transistor 4 is connected to a second bit line 24. The collectors are further coupled to a row select line 26 through load PNP transistors 28 and 30.
The load implements the non-linear resistance required to maintain reasonable cell differential voltage under both low current standby mode and higher current read/write mode. In a previously developed load arrangement discussed in the article, "Technology Improvement for High Speed ECL Rams", IEDM 86, 468-471, by Ogiue, Odaka, Iwabuchi and Uchida, a well known arrangement is described wherein a PNP transistor is utilized as the load. This arrangement, which also appears in FIG. 1, uses first and second PNP transistor 28, 30 having their emitters 32, 34 connected to the select line 26. A collector 36 of the first PNP transistor is connected to the base 6 of the first multi-emitter transistor 2, the base 38 of the second PNP transistor 30, and the collector 10 of the second multi-emitter transistor 4. The second PNP transistor 30 is similarly connected. In this arrangement, either half of the cell operates as an SCR latch or what is commonly called a thyristor latch. It is characterized by the storage of a large amount of charge in the form of diffusion capacitance in the PNP and NPN transistors when the collector base regions of the PNP and NPN transistors are in saturation. This cell device, as with other prior art devices, described briefly below, is characterized by a fundamental charge storage problem in the base region of PNP and collector region of the multi-emitter NPN transistor. The stored charge occurs in the epi region of the cell. The charge storage results in a long write pulse width and long write recovery time for the cell. In order to write opposite data into the cell, the holes that have been injected into the epitaxial (epi) region or collector of the multi-emitter transistor, must be removed from the side of the cell that is being turned off and supplied to the side of the cell that is turning on or being written into.
An alternative approach to this charge storage problem is shown in FIG. 2 wherein the load is provided by Schottky diodes 40, 42, each of the Schottky diodes being connected in series with a 300-500 ohm resistor 44, 46 and in parallel with a 20K 100K ohm resistor 48, 50. In the standby mode, the cell holds latch using the 100K ohm resistor; sensing occurs through the 300 ohm resistor. When a half cell is to be sensed, the 100K ohm resistor is transparent. This cell provides fast write times, but is alpha particle sensitive.
Alpha particle immunity is an absolute requirement in high speed RAMs. Alpha particles may come from almost any material that is used in the fabrication of high speed RAMs. It was once thought that alpha particles came just from the ceramic package used to mount a high speed RAM. Therefore, the solution attempted was a thick coating of polyimide over the die. Later studies proved that alpha particles may occur in the aluminum or other materials used in RAM fabrication. Because the alpha particles occur in the material of which the product is made, the solution must be provided in the design of the part itself. Historically, any part designed to be alpha insensitive is also relatively harder to write. In order to maximize the speed of a RAM, it is necessary to overcome this deficiency. An effort to overcome the alpha particle problem is disclosed at FIG. 3 which is also taken from the Ogiue article. In this design, a large tantalum oxide Ta.sub.2 O.sub.5 capacitor 52, 54 is placed in parallel with each of the Schottky diodes. However, this design has the deficiency of requiring a very high standby current and the integration of the capacitors 52, 54.
A more recent effort to overcome this deficiency is shown in U.S. Pat. No. 4,580,244, which discloses the circuit shown in FIG. 4. In this design, the collector base junction of the PNP load transistor 28, 30 is clamped with an NPN transistor 56, 58 operating in the inverse mode. That is, each of the transistors 56, 58 has the base tied to the collector to act as a diode. This NPN transistor (56, 58) functions to steal current from the associated lateral PNP transistor 28, 30, in effect robbing base current and lowering the beta of this transistor. Therefore, less charge is stored and it is easier to write using this design. In other words, the configuration of FIG. 4 is really a beta lowering mechanism which basically gives the PNP emitter lower emission efficiency. However the stored charge problem remains due to the fact that the SCR must hold latch for the cell to work.
Thus, a memory cell is needed that can differentiate so that it is alpha hard with trickle currents into it in the standby mode, but when it is being read using higher sense currents, it is easy to write. When a cell is being written or read, enough current can be used so that the alpha particles do not create a problem.